A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica Delay-Cells
M. Kim, S. Choi, and J. Choi
IEEE Symp. VLSI Circuits Dig., Jun. 2015. (accepted)
Our paper entitled "A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells" has been accepted for presentation at the 2015 Symposium on VLSI Circuits held in Kyoto. In this paper, the DLL-based PVT calibrator is proposed to overcome major drawbacks of conventional injection locked clock multipliers. Using the proposed DLL-based calibrator, the VCO can track the frequency change over real-time environmental variations. Also, this clock multiplier achieved a fine frequency resolution by rotationally switching the injecting point of the multi-stage VCO. The clock multiplier was fabricated in a 65-nm CMOS technology, and the active area was 0.041 mm^2.