[Tel] +82-42-350-7558

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop
    Y. Lee, H. Yoon, M. Kim, and J. Choi
   IEEE Symp. VLSI Circuits Dig., Jun. 2016
This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of the calibration can be increased. The measured reference spur and RMS jitter were −59 dBc and 450 fs, respectively, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively.
   Comparison table