School of Electrical & Computer Engineering, UNIST
Combined M.S. - Ph.D
Lab : KAIST E3-2 5214
2015 - 2019
B.S. in Electrical and Computer Engineering, summa cum laude
Ulsan National Institute of Science and Technology (UNIST)
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, accepted for publication.
J. Kim**, H. Yoon**, Y. Lim**, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (** Equally-Credited Authors)
J. Lee, S. Choi, Y. Cho, and J. Choi*, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," Electronics Letters, Mar. 2018.