Heein Yoon
Assistant Professor, School of Electrical Engineering
@UNIST, Ulsan, South Korea, Mar. 2022 – Present
Contact Info.
Email: heein.yoon@unist.ac.kr
Home page: https://acel.unist.ac.kr/
Education
Ulsan National Institute of Science and Technology, Ulsan, Korea
Combined M.S. and Ph.D. in Electrical Engineering,
GPA 4.15/4.3, summa cum laude, 2014.09 – 2019.08
Ulsan National Institute of Science and Technology, Ulsan, Korea
B.S. in Electrical and Computer Engineering,
GPA 4.01/4.3, summa cum laude, 2011.03 – 2014.08
Experience
Senior Engineer at Qualcomm, San Diego, CA, USA
May. 2019 – Feb. 2022
Internship at Qualcomm, San Diego, CA, USA
Aug. 2017 – Feb. 2018 (7 Months)
Publications
Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, accepted for publication.
H. Yoon, S. Park, and J. Choi, "A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration," IEEE J. Solid-State Circuits (JSSC), accepted for publication.
J. Kim*, H. Yoon*, Y. Lim*, Y. Lee, Y. Cho, T. Seong, and J. Choi, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL ···," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019, accepted for presentation. (** Equally-Credited Authors)
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, “Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers,” IEEE International Solid-State Circuit Conference (ISSCC) Dig. Tech. Papers, Feb. 2018.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers”, IEEE J. Solid-State Circuits, vol. 53, no. 2, pp. 375–388.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers”, 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018.
S. Park, H. Yoon, and J. Choi, “An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration,” IEEE Asian Solid-State Circuits (ASSCC), Nov. 2017.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, “A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop for mm-Band 5G Transceivers,” IEEE International Solid-State Circuit Conference (ISSCC) Dig. Tech. Papers, Feb. 2017.
Y. Lee, H. Yoon, M. Kim, and J. Choi, “A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop,” IEEE Symp. VLSI Circuits Dig., Jun. 2016.
H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi, “A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers”, IEEE J. Solid-State Circuits, vol. 51, no. 3, pp. 614–625 Mar. 2016.
H. Yoon, Y. Lee, and J. Choi, “A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 5, pp.289–293, May 2014
Presentation & Poster
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi’s research will be presented at IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2018
H. Yoon, S. Park, and J. Choi’s research presented at IEEE International Solid-State Circuit Conference (ISSCC) SRP Session, Feb. 2017
Invited Talks
“A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers”, ECE seminar at UC San Diego (UCSD), Hosted by Prof. Ian Galton, Feb. 23, 2018
Awards and Honors
25th Samsung HumanTech Paper Award, Bronze Prize
in Circuit Design, Feb. 2019
SSCS Predoctoral Achievement Award Winner, Feb. 2019
ISSCC Student Research Preview (SRP) Award Winner, Feb. 2018
24th Samsung HumanTech Paper Award, Honorable mention
in Circuit Design, Feb. 2018
IEEE SSCS Student Travel Grant Award (STGA), 2017. LINK
23rd Samsung HumanTech Paper Award, Bronze Prize
in Circuit Design, Feb. 2017
Global Ph.D. Fellowship Program (2015.03 - Present)
Nine Bridge and Star Fellowship Program (2014. 09 - 2015. 02)
Granted Patents
J. Choi, H. Yoon, and S. Park, Injection-Locked Multi-Clock-Frequency Generator Using a Time-Interleaved Multi-DCO Calibrator, Patent No.:10-1852832, Apr. 23, 2018. (Granted)
J. Choi, J. Lee, and H. Yoon, Phase Generator Based on Delay Lock Loop Circuit and Delay Locking, Patent No.:10-1628160, Jun. 01, 2016 (Granted)
J. Choi, Y. Lee, and H. Yoon, PVT Calibrating Circuit and Method for Injection-Locked Ring-Oscillators, Patent No.:10-1548256, Aug. 24, 2015. (Granted)
J. Choi, and H. Yoon, Wideband LC-VCO Using a Transconductance-switching Technique, Patent No.: 10-1527291, Jun. 2, 2015. (Granted)
Filed Patents
J. Choi, H. Yoon, S. Park, and J. Kim, Frequency Discriminator Based on Delay Locked Loop, Application No.:10-2018-0020047, Feb. 20, 2018. (Filed)
J. Choi, Y. Lee, and H. Yoon, A Low-Reference-Spur and Low-Jitter Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop with High Calibrating Precision, Application No.:10-2017-0008449, Jan. 18, 2017. (Filed)
J. Choi, H. Yoon, and Y. Lee, Apparatus for High Frequency Division and the Calibration Logic for Correcting Divider’s Operation, Application No.:10-2015-0108933, Jul. 31, 2015. (Filed)