CONTACT

[Tel] +82-42-350-7558
[Address]

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

 
Jooeun Bang
School of Electrical Engineering, KAIST
Ph.D., 2020 ~ Present

   Contact Info. 
Lab : KAIST E3-2 5214
Email : jebang@kaist.ac.kr
   Education 
2018 - 2020
M.S. in Electrical and Computer Engineering,
Ulsan National Institute of Science and Technology
2014 - 2018
B.S. in Electrical and Computer Engineering
Ulsan National Institute of Science and Technology
 
   Publications
Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), accepted for publication, invited from IEEE 2019 Symp. VLSI Circuits.
J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi*, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.