CONTACT

[Tel] +82-42-350-7558
[Address]

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

Jeonghyun Lee
School of Electrical Engineering, KAIST
Ph.D., 2020.03 ~ Present

Contact Info.
Lab : KAIST E3-2 5214
Email 1 : jeonghyun@kaist.ac.kr
Email 2 : qazplm95147@gmail.com
Education
2017.03 - 2020.02
M.S. in Electrical and Computer Engineering
Ulsan National Institute of Science and Technology.
2013.03 - 2017.02
B.S. in Electrical and Computer Engineering, graduated with top honors
Ulsan National Institute of Science and Technology.
Publications
Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using ...," IEEE International Solid-State Circuits  Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), accepted for publication, invited from IEEE 2019 Symp. VLSI Circuits.
J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019, accepted for presentation.
Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits, Sep. 2018.
Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153 fs RMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018.
J. Lee, S. Choi, Y. Cho, and J. Choi*, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," Electronics Letters, Mar. 2018.
Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov. 2017.
 
Y. Lim, J. Lee, S. Park, and J. Choi, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May. 2017.
Presentation
J. Lee, J. Bang, Y. Lim, S. Yoo, and J. Choi's research will be presented at IEEE Symp. VLSI Circuits Dig., Jun. 2019.
Domestic Patents
J. Choi, Y. Lim, J. Lee "DIGITAL-ANALOG HYBRID LOW DROPOUT REGULATOR" (Apply Num.: 10-2018-0058976)
 
J. Choi, Y. Lim, J. Lee "APPARATUS AND METHOD FOR LOW DROP-OUT VOLTAGE REGULATING" (Apply Num.: 10-2017-0005927)
Scholarship
Global Ph.D Fellowship Program (2018.03 - Present)
Awards
2016 16th IEEE RF/Analog IC Workshop, Best Paper Award (2016.09)