CONTACT

[Tel] +82-42-350-7558
[Address]

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

Juyeop Kim
School of Electrical Engineering, KAIST
Ph.D., 2020 ~ Present

Contact Info.
Lab : KAIST E3-2 5214
Email : juyeop@kaist.ac.kr
Education
2017.03 - 2020.02
M.S. in Electrical & Computer Engineering
Ulsan National Institute of Science and Technology.
2013.03 - 2017.02
B.S. in Electrical & Computer Engineering
Ulsan National Institute of Science and Technology.
Publications
Y. Lim**, J. Kim**, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (** Equally-Credited Authors)
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, Dec. 2019, invited from IEEE 2019 International Solid-State Circuits Conference (ISSCC).
S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, Aug. 2019.
J. Kim**, H. Yoon**, Y. Lim**, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (** Equally-Credited Authors)
 
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
 
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits, Sep. 2017, published online. 
 
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE ISSCC Dig. Tech. Papers, Feb. 2017.
 
Awards
 
25th Samsung HumanTech Paper Award, Bronze Prize in Circuit Design, Feb. 2019.
 
24th Samsung HumanTech Paper Award, Honorable mention in Circuit Design, Feb. 2018.