[Tel] +82-42-350-7558

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

Suneui Park
School of Electrical Engineering, KAIST
Ph.D., 2020 ~ Present

Contact Info.
Lab : KAIST E3-2 5214
Email :
2017.03 - 2020.02
M.S. in Electrical & Computer Engineering,
Ulsan National Institute of Science and Technology.
2013.03 - 2017.02
B.S. in Electrical & Computer Engineering, summa cum laude
Ulsan National Institute of Science and Technology.
S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, accepted for publication.
H. Yoon, S. Park, and J. Choi, "A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration," IEEE J. Solid-State Circuits (JSSC), accepted for publication.
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits  Conference (ISSCC), Feb. 2018, accepted for presentation.
S. Park, H. Yoon, and J. Choi*, "An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2017, accepted for presenatation.
Y. Lim, J. Lee, S. Park, and J. Choi, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May. 2017.