Taeho Seong

School of Electrical Engineering, KAIST

Postdoctoral Researcher

 

Contact Info.

Lab : KAIST E3-2 5214

Email : poncelet@unist.ac.kr

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Education

2011 - 2015

B.S. in Electrical & Computer Engineering, summa cum laude

Ulsan National Institute of Science and Technology.

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2015 - 2021

School of Electrical & Computer Engineering, UNIST

Combined M.S. - Ph.D

 

Publications

J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.

 

C. Hwang=, H. Park=, Y. Lee, T. Seong, J. Choi*, "A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM,"  IEEE J. Solid-State Circuits (JSSC), early access. (= Equally-Credited Authors)

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C. Hwang=, H. Park=, T. Seong, J. Choi*, "A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

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H. Park=, C. Hwang=, T. Seong=, Y. Lee, J. Choi*, "A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), accepted for publication, invited from IEEE 2019 Symp. VLSI Circuits.

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J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, accepted for publication.

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S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, accepted for publication.

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T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A 320-fs RMS-Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE Journal of Solid-State Circuits, accepted for publication.

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S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019, accepted for presentation.

 

Y. Lee, T. Seong, S. Yoo, and J. Choi, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique," IEEE Journal of Solid-State Circuits (JSSC), Oct. 2017, accepted for publication.

 

T. Seong, Y. Lee, S. Yoo, and J. Choi, "Ring-DCO based All-Digital PLL Using a Fast Phase-Error Correction Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018, accepted for presentation.

 

T. Seong, Y. Lee, S. Yoo, and J. Choi, "A –242-dB FOM and –71-dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL," IEEE Symp. VLSI Circuits Dig., Jun. 2017.

 

S. Yoo, S. Choi, T. Seong and J. Choi, "An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals," IEEE Microwave and Wireless Components Letters (IEEE MWCL), Dec. 2015.

 

M. Kim, S. Choi, T. Seong, and J. Choi, "A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay Cells," IEEE J. Solid-State Circuits, Oct. 2015.

 

Y. Lee, M. Kim, T. Seong, and J. Choi, "A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs" IEEE Transactions on Circuits and Systems I (IEEE T-CAS I), Mar. 2015.

 

T. Seong, J. Kim, and J. Choi, "Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers," IEEE Transactions on Circuits and Systems I (IEEE T-CAS I), Mar. 2015

 

T. Seong, Y. Lee, and J. Choi, "An Ultra-Low In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration," IEEE Transactions on Circuits and Systems II (IEEE T-CAS II), Sep. 2014.