CONTACT

[Tel] +82-42-350-7558
[Address]

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

Younghyun Lim
School of Electrical & Computer Engineering, UNIST
Combined Master's - Doctoral Program, 2015.03 ~ Present

 

Contact Info.
Lab : UNIST EB3 603-2
Email : younghyun@unist.ac.kr, dudgus0262@gmail.com
 
Education
2011.03 - 2015.02
B.S. in Electrical and Computer Engineering
Ulsan National Institute of Science and Technology.
 
​​Research Interest
1. Power management IC (PMIC)
 - Low-dropout (LDO) regulators 
 - Voltage and current references
2. Frequency synthesizer
 - Sub-sampling phase-locked loop (SSPLL)
Experience
2019.09 - 2020.03
Internship at Qualcomm, San Diego, CA, USA.
Publications
First Author
Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
J. Kim=, H. Yoon=, Y. Lim=, Y. Lee, Y. Cho, T. Seong, and J. Choi, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (= Equally-Credited Authors)

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2018.

Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov. 2017.
 
Y. Lim, J. Lee, S. Park, and J. Choi, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May. 2017.
Y. Lim, J. Lee, S. Park, and J. Choi, "An External-Capacitor-Less High-PSR Low-Dropout Regulator Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018
Co-Author
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, accepted for publication.
J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), accepted for publication, invited from IEEE 2019 Symp. VLSI Circuits.
J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.
 

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits (JSSC), Mar. 2019.

​​S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim, and J. Choi, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "153 fs RMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018. 
 
K. Lim, S. Lee, Y. Lee, Y. Lim, C. Song, J. Seong, J. Choi, and S. Han, "A 65nm CMOS 2×2 MIMO Multi-band LTE RF Transceiver for Small Cell Base Stations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2018.
 
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim and J. Choi, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
S. Choi, S. Yoo, Y. Lim, and J. Choi, "A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector," IEEE Journal of Solid-State Circuits (JSSC), Aug. 2016.
H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi, "A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers", IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016.
K. J. Han, Y. Lim, and Y. Kim, "A performance analysis for interconnections of 3D ICs with frequency-dependent TSV model in S-parameter", Journal of Semiconductor Technology and Science (JSTC), Oct. 2014.
 
Presentation & Poster
 
Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi's research has been accepted for presentation at the 2018 ISSCC Student Research Preview (SRP) session
 
Y. Lim, J. Lee, S. Park, and J. Choi's research has been accepted for presentation at the 2018 ASP-DAC
 
Y. Lim, J. Lee, and J. Choi's research has been accepted for presentation at the 16th IEEE RF/Analog IC Workshop
 
Scholarship
 
Global Ph.D Fellowship Program (2016.03 - Present)
 
Domestic Patents
 
J. Choi, Y. Lim, J. Lee "DIGITAL-ANALOG HYBRID LOW DROPOUT REGULATOR" (Apply Num.: 10-2018-0058976)
 
J. Choi, Y. Lim, J. Lee "APPARATUS AND METHOD FOR LOW DROP-OUT VOLTAGE REGULATING" (Apply Num.: 10-2017-0005927)
 
J. Choi, Y. Lim "Power supplying device and Image display apparatus including the same (Apply Num.: 10-2016-0057782)
 
Awards
 
ISSCC Student Research Preview (SRP) Award Winner (2019.02)
25th Samsung Humantech Paper Award, Bronze Prize Award (2019.02)
24th Samsung Humantech Paper Award, Honorable Mention Award (2018.01)
 
2016 16th IEEE RF/Analog IC Workshop, Best Paper Award (2016.09)