CONTACT

[Tel] +82-42-350-7558
[Address]

Bldg. E3-2, Rm. 5214,

291, Daehak-ro, Yuseong-gu, Daejeon

34141, Republic of Korea

Yongsun Lee (이용선)

School of Electrical & Computer Engineering, UNIST

Combined M.S. - Ph.D

 

    Contact Info.

Lab : KAIST E3-2 5214

Email : yslee1394@gmail.com

    Education

2010 - 2014

B.S. in Electrical and Computer Engineering

Ulsan National Institute of Science and Technology (UNIST)

      Publications

Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), Dec. 2019.
J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019.

T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A 320-fs RMS-Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE Journal of Solid-State Circuits (JSSC), accepted for publication, Sep. 2019.
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2019.
S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference Conference (ISSCC), Feb. 2019.
J. Kim=, H. Yoon=, Y. Lim=, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (= Equally-Credited Authors)
Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2018.
Y. Lee, T. Seong, S. Yoo, and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2018.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2018. 
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi*, "A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A -242dB FOM and -75dBc-Reference-Spur Ring-DCO based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
Y. Lee, T. Seong, S. Yoo, and J. Choi*, "A Switched-Loop-Filter PLL with a Fast Phase Error-Correction Technique", 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2018.
Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi*, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Nov. 2017.
T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A –242-dB FOM and –71-dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2017.
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.
Y. Lee, H. Yoon, M. Kim, and J. Choi*, "A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2016.
H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi*, "A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016.
Y. Lee, M. Kim, T. Seong, and J. Choi*, "A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs," IEEE Transactions on Circuits and Systems I (TCAS-I), Mar. 2015.
T. Seong, Y. Lee, and J. Choi*, "An Ultra-Low In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration," IEEE Transactions on Circuits and Systems II (TCAS-II), Sep. 2014.
H. Yoon, Y. Lee, and J. Choi*, "A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core," IEEE Transactions on Circuits and Systems II (TCAS-II), Apr. 2014.

      Patent
 
"Apparatus and Method for Injection Locked Clock Multiply,"  Patent No. 10-2018-0085164, 2018.
 
"Frequency Dividing Circuit," Patent No. 10-2017-0014905, 2017.
 
"Apparatus for PVT Variation Calibration of Ring OSC Based on Injection Locking System and the Method Thereof," Patent No. 10-2015-0031983, 2015.
      Awards and Honors
 
25th Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2019.
 
25th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2019.
 
19th Korea Semiconductor Design Competition, President of Semiconductor Association's Award, Oct. 2018.
 
24th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2018.
 
23rd Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2017.