A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally-Spaced Voltage Comparators and Background Loop-Gain Optimization

 

ICSL’s paper (authors: Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, and Prof. Jaehyouk Choi) “A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally-Spaced Voltage Comparators and Background Loop-Gain Optimization” has been accepted for presentation at 2019 IEEE ISSCC (International Solid-State Circuits Conference) in San Francisco in coming February. ISSCC is called “the Olympic in the field of semiconductor circuit designs” and it is considered to be great honor to present a paper from academia. ICSL has become to stand on a podium four years in a row.

 

Authors: Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, and Jaehyouk Choi

Title: A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally-Spaced Voltage Comparators and Background Loop-Gain Optimization

Conference: 2019 IEEE International Solid-State Circuit Conference (ISSCC)

Presentation date: February, 2019